The present invention relates to a semiconductor memory device and, more particularly, to a flash memory device capable of reducing coupling caused between adjacent memory cells in the same row.
In recent years, application of storage devices such as volatile memories and non-volatile memories are rapidly spread into mobile devices such as MP3 players, portable media players (PMPs), cellular phones, notebook computers, personal digital assistants (PDAs), and the like. Such mobile devices necessitate mass storage devices to provide various functions (e.g., moving figure reproducing function). Many efforts have been made to satisfy such needs. As one of such efforts, a multi-bit memory device has been proposed which stores 2-bit data or more per cell. Below, a memory cell storing multi-bit data is called an MLC. And, the mass storage devices can be implemented to integrate more memory cells per unit area, according to advances in process technologies.
FIG. 1 is a diagram showing a conventional flash memory device. A conventional flash memory device includes a cell array 10, a bit line selector circuit 20, and a page buffer circuit 30. Memory cells constitute a page unit that share a word line (WL). Alternatively, memory cells constitute a string unit serially connected with respect to a bit line. A plurality of string units constitutes a block, which comprises a basic erase unit.
The bit line selector circuit 20 selects either even-numbered bit lines BLe<X> or odd-number bit lines BLo<X> according to the control of a controller circuit 40. This bit line structure is used to reduce current noise that is made during a read operation. Accordingly, in order to read data from all memory cells connected to one word line, a bit line selecting operation for selecting even-numbered bit lines and odd-numbered bit lines through the bit line selector circuit 20 has to be carried out twice. This switching operation is not limited to the read operation. For example, during a program operation, an even page and an odd page are individually selected and programmed sequentially. Switches SW1-SW8 of the bit line selector circuit 20 are each formed of a high-voltage switch.
The page buffer circuit 30 operates as a write driver for a program operation and as a sense amplifier for a read operation. During the program operation, the page buffer circuit 30 supplies a pair of even-numbered and odd-numbered bit lines sequentially with a voltage corresponding to data. When programming an MLC, the page buffer circuit 30 provides LSB page data to respective bit lines and then MSB page data thereto. Accordingly, one latch is connected with a pair of even-numbered and odd-numbered bit lines.
The controller circuit 40 controls the bit line selector circuit 20 to select even-numbered or odd-numbered bit lines based on a column address. A row decoder circuit 50 controls connecting of memory cells to bit lines in response to a row address, and supplies a selected word line with a program voltage, a read voltage, and the like. The row decoder circuit 50 supplies a pass voltage to unselected word lines at a program operation so that connection between selected memory cells and bit lines is maintained.
FIG. 2 is a diagram showing a layout structure of a bit line selector circuit 20 illustrated in FIG. 1. Referring to FIG. 2, gate lines GLi(i=0, 2, . . . , (k-2)) for selecting even-numbered bit lines and gate lines GLj(j=1,3, . . . , (k-1)) for selecting odd-numbered bit lines are formed on a plurality of semiconductor active regions 21. Those skilled in the art will appreciate that switches are described by describing the active region 21. A bit line signal from a latch (e.g., LCH<0>) of a page buffer circuit 30 in FIG. 1 is provided to an even-numbered bit line BLe<0> or an odd-numbered bit line BLo<0> by control signals BLSe and BSLo transferred to the gate lines GL<0> and GL<1> that are formed on the active region 21. In the event that the control signal BLSe has a high level and the control signal BLSo has a low level, the bit line BLe<0> is selected. In the event that the control signal BLSe has a low level and the control signal BLSo has a high level, the bit line BLo<0> is selected. Bit line signals from the page buffer circuit 30 are in turn transferred to odd-numbered or even-numbered bit lines. That is, high-voltage switches (e.g., SW1 and SW2, refer to FIG. 1) are formed by the active region 21 and the gate lines GL<0> and GL<1>.
FIG. 3 is a diagram for describing the coupling caused between memory cells 14 sharing the same word line, in the event that the memory cells are programmed in a manner described in FIG. 2. Memory cells MC<0> and MC<2> are programmed when even-numbered bit lines are selected, and then a memory cell MC<1> is programmed to a specific state when an odd-numbered bit line is selected. The coupling effect can be caused through parasitic capacitance Cx between floating gates of adjacent memory cells MC<0> and MC<2> when the memory cell MC<1> is programmed. Accordingly, threshold voltages of the memory cells MC<0> and MC<2> become higher than a previously programmed threshold voltage.
Unintended programming is made at unselected memory cells due to the coupling effect that causes variation of a threshold voltage of a memory cell, which is called “program disturbance.” A program disturbance problem of a flash memory device is disclosed in U.S. Pat. No. 5,867,429 entitled “HIGH DENSITY NON-VOLATILE FLASH MEMORY ADVERSE EFFECTS OF ELECTRIC FIELD COUPLING BETWEEN ADJACENT FLOATING GATES,” hereinafter the “the '429 patent.” In accordance with a program method disclosed in the '429 patent, a threshold voltage distribution is widened due to the coupling effect, so that a margin between threshold voltage distributions is reduced. However, the '429 patent necessitates an additional program operation for adjusting a threshold voltage distribution after performing a conventional program operation. As a result, a program time is increased and complicated control is needed.
Accordingly, a technique is required which can block the coupling effect caused between memory cells, without requiring additional program operations.